library verilog;
use verilog.vl_types.all;
entity encrypt_47_top is
    port(
        clk             : in     vl_logic;
        button          : in     vl_logic;
        led             : out    vl_logic;
        uart_txd        : out    vl_logic;
        dig1            : out    vl_logic;
        dig2            : out    vl_logic;
        segment1        : out    vl_logic_vector(6 downto 0);
        segment2        : out    vl_logic_vector(6 downto 0)
    );
end encrypt_47_top;
